Residual Saw Damage in Silicon Wafers and Its Influence on MOS Capacitance Relaxation

Residual saw damage in silicon surfaces and its influence on MOS capacitance relaxation is discussed. Experiments are conducted to gain information on the influence of silicon process parameters on MOS capacitance relaxation. Process parameters investigated include crystal slicing, wafer cleaning and wafer polishing. The main results of this investigation include evidence about saw damage in the silicon surface and its variation with different slicing and polishing procedures. It is also found that the amount of saw damage is larger in wafers cut from the tail-end relative to wafers cut from the seed-part of the crystal. Based on the results obtained, recommendations are made about future activities of the contract work.