A Class of Testable Gate Network Realizations for Logic Functions.

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Abstract:

By assuming that the functions realized by certain subnetworks of certain gate networks realizing an arbitrary logic function are known, techniques to derive tests to detect faults in these networks are derived. Author

Author(s):
Reddy, Sudhakar M.
Author Organization(s):
IOWA UNIV IOWA CITY DEPT OF MATHEMATICS
Descriptive Note:
Technical rept.,
Supplementary Note:
Report on the Theory and Applications of Automation Theory.
Pagination:
0017

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
TR-57
Contract/Grant Number(s):
N00014-68-C-0500
 Subject Terms
Joint Capability Areas:
JCA_6.1_Information Transport; JCA_6_Net Centric
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*LOGIC CIRCUITS, *GATES(CIRCUITS), COMPUTER LOGIC, BINARY ARITHMETIC, VECTOR SPACES, SET THEORY, THEOREMS
Field(s)/Group(s):
Electrical and Electronic Equipment, Theoretical Mathematics
Keyword(s):
AUTOMATA, BOOLEAN FUNCTIONS, FAULT DETECTION
Report Date:
1972 May 01