One Digit Decimal Adder,

reportActive / Technical Report | Accession Number: AD0744170 | Need Help?

Abstract:

The authors analyze a method for construction of a combination adder to yield a savings of logic elements. The second stage of the adder, the sum correction section, is changed. If this method is applied to adders based on combination accumulating elements, an even greater saving of equipment is produced due to the presence of inverted variables. An example of construction of a decimal adder in 8421 code is presented. Author

Author(s):
Kakurin, N. Ya. ; Vansilenko, Yu. A.
Author Organization(s):
FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OHIO
Supplementary Note:
Unedited rough draft trans. of Pribory i Sistemy Avtomatiki (USSR) n13 p71-74 1970.
Annotation:
One Digit Decimal Adder--Translation.
Pagination:
0009

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
FTD-HC-23-1797-71
 Subject Terms
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*LOGIC CIRCUITS, SHIFT REGISTERS, DIGITAL COMPUTERS, USSR
Field(s)/Group(s):
Computer Hardware
Keyword(s):
LOGIC DESIGN, *ADDING CIRCUITS, TRANSLATIONS
Report Date:
1972 Apr 03