Digital Logic Simulator.

Digital Logic Simulator DLS is a CDC 6600 computer program which simulates synchronous and asynchronous networks of digital logic elements. It is used at Air Force Institute of Technology to verify digital logic designs. DLS uses a state variable model which associates time delays with all elements. Thus, the effects of propagation delays on circuit behavior can be analyzed. DLS has four operation modes which allow the user to test circuits at various levels of complexity. A complete users manual is included in the thesis which describes the detailed features, capabilities, and language specifications for DLS. Author