BINARY PARALLEL SUMMATOR WITH THROUGH TRANSFER

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Abstract:

A binary parallel summator with through transfer, utilizing the impedance principle of ferrite work is composed of paraphase ferrite registers of the first and second addends, and is connected by census bus-bars for realization of the logical function of addition according to the two modulus with ferrites of the summator. Census bus bars, the states of which for obtaining sums in a given place and the transfer and its inversion in the following place, pass through the ferrites of the sum register, and are connected with the in versed and direct output of the transfer of the preceeding place. They are distinguished by the fact that, for the purpose of enlarging the re liability, compensation bus-bars pass through the ferrites of the registers and the summator.

Author(s):
Afinogenov, L. P. ; Kolosov, V. G.
Author Organization(s):
FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OH
Supplementary Note:
Trans. from Russian Patent Nr. 142818 (642726/26, January 6, 1960), 1960, pp 1-3.
Pagination:
0008

Security Markings

DOCUMENT & CONTEXTUAL SUMMARY

Distribution:
Approved For Public Release
Distribution Statement:
Approved For Public Release; Distribution Is Unlimited.

RECORD

Collection: TR
Identifying Numbers
Report Number(s):
FTD-TT-63-175
Monitor Series:
FTD
 Subject Terms
Communities of Interest:
No COI(s) Identified
Descriptor(s):
*COMPUTER LOGIC, *BINARY PROCESSORS, USSR, REGISTERS(CIRCUITS), TRANSLATIONS, MAGNETIC CORES
Field(s)/Group(s):
Computer Hardware
Keyword(s):
FOREIGN REPORTS
Report Date:
1963 Mar 01