DELAY LINE

A delay line circuit is described. Readout from one capacitor and recording from the preceding cascade on the next capacitor occurs during each cycle in each cascade of the delay line. This special feature of the circuit makes it possible to obtain the same accuracy of reproducing a function as in known circuits with half the number of triodes, or with the same number of triodes and same commutation speed of the contacts to obtain a high accuracy of reproducing a function on the delay-line output. Author