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Accession Number:

AD1183547

Title:

Rapid Modeling and Analysis Framework for Full-Chip/Package/Board Layout Automation

Author(s):

• Jiao, Dan

Author Organization(s):

• Purdue University

Report Date:

2022-10-01

Abstract:

Rapid and accurate layout modeling and analysis at a scale as large as full-chip, complete package and whole board is one of the key enablers to the success of machine generated physical layout in fast CPU run time. Existing layout tools lack such a capability, which has resulted in frequent layout failure and time intensive manual correction of the layout. In this work, PI Jiao has developed algorithms and software for rapid and first-principle-accurate full-chip/package/board layout modeling and analysis, and used such a capability to guide layout synthesis in a fast turnaround time.

Document Type:

Conference:

Journal:

Pages:

17

File Size:

2.82MB

Contracts:

Grants:

Descriptors:

Identifiers:

• parasitic extraction
• layout simulation
• first-principles accuracy
• large-scale modeling and analysis

SubjectCategory:

• Mathematical and Computer Sciences
• Mathematical and Computer Sciences
• Electrotechnology and Fluidics

Communities of Interest:

• Advanced Electronics

Distribution Statement:

Approved For Public Release

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