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A Quaternary Logic Encoder-Decoder Circuit Design Using CMOS,
CALIFORNIA UNIV DAVIS INTEGRATED CIRCUITS LAB
A binary-to-quaternary encoder and quaternary-to-binary decoder circuit pair is described as designed in a 5-volt CMOS technology. These circuits communicate with logical currents. Using model parameter values for a standard 5-micron polysilicon gate process technology and 10 microamp logical currents, we have simulated propagation delays of about 20 ns from binary encoder input to binary decoder output. With the encoder using scaled-up logical currents and driving a 100 pF load on the decoder input to simulate communication between chips, we observe simulated worst-case delays of about 35ns. Author
This article is from 'Proceedings of the International Symposium on Multiple-Valued Logic (13th) Held at Kyoto, Japan on May 23-25, 1983,' AD-A136 457, p190-195.