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Accession Number:
ADP002345
Title:
Pulse-Train Residue Arithmetic Circuit Using Multiple-Valued Charge-Coupled Devices and Its Application to Digital Filter,
Corporate Author:
HACHINOHE INST OF TECH (JAPAN) DEPT OF ELECTRICAL ENGINEERING
Report Date:
1983-05-01
Abstract:
A new design method of compact residue arithmetic circuit using multiple-valued charge-coupled devices CCDs is proposed. The multiple-valued ring counter for the residue arithmetic is designed by using the CCDs. Because the structure of the counter is very simple, it is effectively used as the basic component to construct the residue arithmetic circuit. The modulo-m addition is performed by shifting the modulo-m multiple-valued ring counter, and the coefficient multiplication is done by converting the multiple-valued code between the counters. The most important advantages of the proposed adder and multiplier are the compact hardware and the uniform operating time, so that these arithmetic circuits can be effectively employed for the pipelining digital signal processing system. Finally, it is demonstrated that the hardware complexity of the digital filter constructed with the quaternary logic CCDs can be reduced to 70 compared with the corresponding binary implementation. Author
Supplementary Note:
This article is from 'Proceedings of the International Symposium on Multiple-Valued Logic (13th) Held at Kyoto, Japan on May 23-25, 1983,' AD-A136 457, p146-151.
Pages:
0006
File Size:
0.00MB
