UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY INFORMATION SCIENCES INST
This report presents a method for automatic systhesis of asynchronous digital systems from high-level data flow specifications. We presents an extended data flow model that accurately reflects the behavior of the asynchronous components so that the data flow specification can be directly mapped into a hardware realization. In addition, we develop a timing model for the basic asynchronous building blocks and show how to derive the timing parameters of a composed systems. This timing model can also be used at the data flow level, allowing designers to explore various design alternatives. We then describe a number of applications of the data flow specification for high-level synthesis such as schemes for resource sharing local transformations for data flow description optimization, and allocation and sequencing of operations for given resources. Finally, we present two examples using this synthesis method. The effectiveness of the data flow specification and performance analysis has been demonstrated from the areas and the simulation of actual layouts generated using an industrial standard cell library and commercial CAD tools. Asynchronous circuitssystems, Data flow graph, Token, Micropipelines, Handshaking protocol, Resource sharing, Algorithmic transformations, Sequencing and allocation.