The design of a high-speed 250 million 32-bit floating point operations per second two dimensional systolic array composed of 16 bitslice microsequencer structured processors will be presented. System design features such as broadcast data flow, tag bit movement, and integrated diagnostic test registers will be described. The software development tools needed to map complex matrix-based signal processing algorithms onto the systolic processor system will be described. Keywords Microsequencer, Algorithms, and Systolic architecture.
Professional paper for period ending Aug 87,
Presented at the SPIE International Technical Symposium, 17-21 Aug 87, San Diego, CA.