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Accession Number:
ADA056534
Title:
Design of Digital Systems Using Self-Checking Alternating Logic.
Corporate Author:
ILLINOIS UNIV AT URBANA-CHAMPAIGN COORDINATED SCIENCE LAB
Report Date:
1977-10-01
Abstract:
This thesis presents analysis of the application of alternating logic to the design of self-checking systems. In particular, results are presented in the areas of combinational logic, sequential logic, self-checking alternating logic modules, self-checking alternating logic checker design, and self-checking alternating logic system design. The necessary and sufficient conditions for a self-dual combinational network to be self-checking are developed. An analytic technique for evaluating if any self-dual network is self-checking is given. A memory efficient approach for the design of self-checking alternating logic sequential machines is presented. Various techniques of checker design for self-checking alternating logic are discussed. The requirements of the hardcore portion of general self-checking systems is given. Minority modules are shown to be sufficient to convert any NAND or NOR network to a self-checking alternating logic network.
Descriptive Note:
Doctoral thesis,
Pages:
0124
Contract Number:
DAAB07-72-C-0259
File Size:
41.61MB
