DID YOU KNOW? DTIC has over 3.5 million final reports on DoD funded research, development, test, and evaluation activities available to our registered users. Click
HERE to register or log in.
Accession Number:
ADA010719
Title:
Design of Totally Self-Checking Asynchronous Sequential Machines.
Corporate Author:
ILLINOIS UNIV URBANA COORDINATED SCIENCE LAB
Report Date:
1975-05-01
Abstract:
Properties of state assignments and circuit realizations that lead to totally self-checking asynchronous machine designs are studied. The state variables and the outputs are encoded so that all single and unidirectional faults cause the machine to assume a noncode state or output. Several state assignment methods are presented. One is the two-rail assignment where the feedback lines are checked with a two-rail checker tree. It is shown that any two-rail checker cannot be used because the state assignment does not in general have all the two-rail codewords. Therefore a checker tree that can be checked by the state assignment code must be selected. An algorithm for finding such a tree is presented. The effect of a fault on the encoded outputs is studied. A self-checking circuit produces a noncode output for at least one code space input. It is shown that a self-checking asynchronous machine will produce a noncode output for at least one input sequence which occurs under normal operation. For this design, the destination sets of each input column of the flow table are encoded with a constant weight or another unordered code. Redundancies in the code and in the realization are discussed. It is shown that extra outputs can be used for the detection of primary input faults and for a class of flow tables for faster fault detection.
Descriptive Note:
Technical rept.,
Pages:
0121
Contract Number:
DAAB07-72-C-0259
File Size:
0.00MB
