So far it has been thought that there do not exist efficient codes suitable for error control in bit wise logical computations. This was basically due to certain negative results established by previous researchers. In this thesis this problem is investigated in a new framework. A crucial assumption that led to the negative results established in a new framework. A crucial assumption that led to the negative results is found unnecessary and hence discarded. Then a class of codes is exhibited and shown to be useful for error control. Furthermore it is shown that the efficiency of the proposed scheme is asymptotically optimum and also far better than the earlier known scheme. The usefulness of this technique is then extended to the design of fault-tolerant arithmetic processors. There has been extensive work done toward the design of fault-tolerant combinational logic networks. A new formulation is given to this problem and several results are established which identify the equivalence in redundancies of fault-tolerant realizations and hazard-free realizations. Author
Report on The Theory and Applications of Automaton Theory.