Several techniques to realize networks for n-variable logic functions are given such that the fault detecting sets under the assumption that single gates are faulty have n4 members and also these fault detecting sets are independent of the function being realized. These networks use two input Exclusive OR gates and AND gates. Techniques to design networks with devices realizing m-input even parity functions and AND gates are also given which require fault detecting test sets, that are independent of the function being realized, with n 2 to the mth power members. Techniques to design the checker and the network to generate the test sets are also given. Author
Report on the Theory and Applications of Automation Theory.