The transistorized single-pulse delay line is described. The authors intent was to design a general-purpose, stable delay line which could operate at cycling frequencies well above the maximum for ferrite delay lines. A detailed description is given of the circuit operation and design calculations for each stage are presented. Theoretically, the line can operate at up to 8 MHz actual tests at 3 MHz have been made.
Edited trans. of Radiotekhnika (USSR) v23 n6 p51-62 1968, by H. Peck.