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A Method of Test Generation for Verification of Wiring Correctness,
POZNAN TECHNICAL UNIV (POLAND) REGIONAL COMPUTER CENTER
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The paper presents a method of test generation for any multiterminal wiring network, such as printed circuit board, computer backpanel wiring etc. The method is based on the minimization of the test generated by examining the correct network with computer-controlled tester. Three-valued algebra was used. In comparison with more straightforward algorithm based on the adjacency matrix, lower space complexity has been achieved - On rather than Osq. n. Author
APPROVED FOR PUBLIC RELEASE