Read/Write Memory Architecture Employing Closed Ring Elements
Patent, Filed 30 Sep 1998, patented 19 Oct 1999
DEPARTMENT OF THE NAVY WASHINGTON DC
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This patent discloses a memory architecture for a regular array of non-volatile ferromagnetic random access annular memory elements which can be based on the giant magnetoresistance GMR effect. A first sense row in the array connects the memory elements with strips which are staggered so that each memory element is connected through its upper surface to the memory element on one side and through the lower surface to one on the other side. Running transverse to the first sense row is a word line made up of a series of wires passing in magnetic field producing proximity to the memory elements along a column of the array and not being in electrical contact with the memory elements. The strips of the word line are staggered so they similarly produce a meandering conductive pathway through the word line from one side of the array to the other in series. The wires of the word line can pass through the open core of the annular element or the wires can pass adjacent to the memory elements. A third addressing mechanism in the form of an additional bit line provides added flexibility for the magnetic switching. The bit line is arranged parallel to the sense row and the strips of the bit line are again staggered so that each wire is connected through its top contact to the wire on one side and through its bottom contact to the wire on the other side. This bit line can be used in combination with or in place of the sense row for magnetic switching when it is further used in combination with the word line. Magnetic switching can be done by the word line and the bit line without using the sense line current. In a further embodiment the memory element has an incubative nonmagnetic memory layer so the memory element becomes a magnetic tunnel junction.
- Computer Hardware