Multiplexing/Demultiplexing System for Asynchronous High and Low-Speed Data.
Patent, Filed 13 Aug 96, patented 7 Jul 98,
DEPARTMENT OF THE NAVY WASHINGTON DC
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A system and method are provided for multiplexingdemultiplexing asynchronous high-speed digital data and asynchronous low-speed digital data. A first digital signal processor DSP receives complete low-speed data messages and is programmed to assemble each complete message into data blocks in accordance with a block format. Each data block is identical in size and includes provisions for a header that identities the data assembled therein. A second DSP has a plurality of IO ports, each of which has a direct memory access DMA associated therewith. One of the IO ports is coupled to the first DSP to receive each complete message assembled into data blocks. The other IO ports are coupled to a second plurality of channels transmitting asynchronous high-speed digital data. The DMAs associated with the other IO ports are configured to assemble the high-speed data into data blocks in accordance with the same block format used for the low-speed messages. The second DSP is coupled to a data recorder so that each complete message assembled in block format and the high-speed data assembled in block format are transmitted to the data recorder when it is operated in the record mode. The first DSP can have an IO port thereof coupled to the data recorder. The DMA associated with this IO port is configured to route the data blocks passed thereto in accordance with the header associated with the data blocks when the data recorder is operated in the playback mode.
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