Method of Making Buried Gate Insulator Field Effect Transistor
Patent, Filed 7 Oct 96, patented 6 Jan 98
DEPARTMENT OF THE NAVY WASHINGTON DC
Pagination or Media Count:
A buried, gate insulator field effect transistor is disclosed. It comprises a source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate and a protective silicon dioxide covering layer. Windows are excised into this covering layer to allow electrical connection to the source, substrate, drain, and gate. The substrate and gate are vertically aligned in the resulting structure. The source, drain and gate are fabricated from a doped, semiconductor of one polarity while the substrate is fabricated from doped semiconductor of the opposite polarity. The gate insulator layer is fabricated by implanting an element or elements selected from Group V, VI or VII into the semiconductor to form a semiconductor-compound insulator. Methods of fabricating this device are also disclosed. In one embodiment the device is fabricated on an insulating base layer. The gate is formed next to me base. In a second embodiment, no base is used. The gate insulator is formed between the gate and substrate. In both cases the gate insulator is formed within the semiconductor in a buried and protected mode.
- Electrical and Electronic Equipment