Digital Circuit for Generating a Clock Signal.
Patent, Filed 31 Jul 95, patented 23 Jul 96,
DEPARTMENT OF THE NAVY WASHINGTON DC
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A digital circuit comprising a pair of D Flip-Flops which synchronize an incoming NRZ L serial data stream to an external ten megahertz clock signal. The combination of a third D Flip-Flop and an EXCLUSIVE-NOR gate generates a clear pulse whenever a change of state occurs within the synchronized serial data stream. This clear pulse is supplied to a ten state machine resetting the state machine to state SO. When the state machine transition to state 54 the state machine generates an enable signal which is supplied to a toggle Flip-Flop enabling the Flip-Flop allowing the Flip-Flop to change state. The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state. At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop. This results in one megahertz clock signal at the output of the toggle Flip-Flop which is synchronized to the incoming serial data stream.
- Electrical and Electronic Equipment
- Test Facilities, Equipment and Methods