Accession Number:

ADD018241

Title:

Serial Bit Pattern Recognizer System.

Descriptive Note:

Patent, Filed 21 Sep 94, patented 17 Oct 96,

Corporate Author:

DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s):

Report Date:

1995-10-17

Pagination or Media Count:

11.0

Abstract:

A recognizer system having a transmitter for transmitting and a receiver for receiving a serial stream of bits that includes data bits and a predetermined bit pattern. The recognizer system recognizes the predetermined bit pattern A bit of the serial stream of bits is directly inputted from the receiver into a memory due to a clock pulse on the memory. The memory is programmed with decision tree statements of a decision tree. A initial state value, stored in a latch, is also inputted, from the latch, into the memory, due to the clock pulse on the memory. A next state value is immediately outputted from the memory. The outputted next state value replaces the initial state value stored in the latch, due to a delayed clock pulse on the latch. The next state is available to the memory. A signal bit is also outputted from the memory to a user device for the digital data. The system continues until a predetermined bit pattern produces a final state of a decision tree out of the memory. At that time a signal bit, of value one, indicates that the predetermined bit pattern has been received from the receiver and allows the user device to receive data hits from the receiver.

Subject Categories:

  • Computer Hardware
  • Cybernetics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE