Method for Fabricating Self-Aligned Gate Diffused Junction Field Effect Transistor.
Patent, Filed 28 Aug 92, patented 28 Sep 93,
DEPARTMENT OF THE NAVY WASHINGTON DC
Pagination or Media Count:
A method for fabricating a self-aligned, gate diffused junction field effect transistor is provided which includes the steps of forming an n-type layer on an indium phosphide, semi-insulating substrate forming spaced apart sourcedrain metal contacts on the n-type layer forming a metal gate on the n-type layer between the spaced apart sourcedrain contacts, where the metal gate is insulated from the sourcedrain contacts and includes a metallic p-type dopant material and forming a p-type region in the n-type layer beneath the metal gate so that the gate contact and the p-type region have coincident boundaries with respect to each other at the surface of the n-type layer. The method may also be employed to manufacture a bipolar transistor by allowing the self-aligned and diffused p-type region to extend through the n-type layer to the semi-insulating substrate.
- Electrical and Electronic Equipment
- Electricity and Magnetism