Circuitry for Compensating for Transistor Parameter Mismatches in a CMOS Analog Four-Quadrant Multiplier.
Patent, Filed 11 Apr 91, patented 17 Mar 92,
DEPARTMENT OF THE NAVY WASHINGTON DC
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The present invention provides a circuit for eliminating quadratic and offset errors in the output of a CMOS four-quadrant analog multiplier. These errors are eliminated by feedback circuits that each include one or more CMOS four-quadrant analog multipliers.
- Electrical and Electronic Equipment