Non-Volatile Memory Cell With Ferroelectric Capacitor Having Logically Inactive Electrode.
Patent,Filed 6 Mar 90, patented 6 Aug 91,
DEPARTMENT OF THE NAVY WASHINGTON DC
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The ferroelectric capacitor in each memory cell of an array has a logically inactive electrode plate maintained at a fixed voltage level and an opposed electrode plate coupled through a switching transistor, turned on by address signals, to a bit line through which the polarization of the capacitor is logically controlled to write and store binary logic data therein which is also readout through the same bit line at a different time during a logic restoring read operation. The ferroelectric material has sufficient conductivity to maintain the electrodes at nearly equal potentials. Author
- Electrical and Electronic Equipment
- Electricity and Magnetism