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Accession Number:
ADD014995
Title:
Insulator Assisted Self-Aligned Gate Junction.
Descriptive Note:
Patent, filed 30 Oct 90, patented 30 Apr 91,
Corporate Author:
DEPARTMENT OF THE NAVY WASHINGTON DC
Report Date:
1991-04-30
Pagination or Media Count:
8.0
Abstract:
A high transconductance, low capacitance, low leakage compound semiconductor junction field effect transistor JFET enhances the low leakage current while having the advantages of a self-aligned JFET including low capacitance and low source-drain resistance. the diffused junction of the JFET is totally covered during the process of manufacture. An n channel on a substrate has a layer of photoresist placed over it and exposed to leave a predefined pattern of photoresist. The patterned photoresist is used as a mask so that part of the n-channel layer is etched down to a desired depth leaving a wedge-shaped region. A layer of insulator, such as silicon dioxide, is deposited over the entire substrate and sides of the w edge-shaped region in insulator regions. Next, the photoresist is then removed. A p diffusion or implant is performed in the wedge-shaped region to create a p n-junction system which is the gate region of the JFET. The p n junction system sides are covered the insulator regions of silicon dioxide unlike the opened-junction of the conventional self-aligned gate JFET. Next, the gate patterned metal is deposited on top of the p n junction system and partially on the silicon dioxide insulator regions. Using the patterned gate metal as a mask, the silicon dioxide layer is removed. Source and drain metals are then self-aligned evaporated. The JFET has potential use in microwave, millimeter-wave and optical electronic circuits. Author
Distribution Statement:
APPROVED FOR PUBLIC RELEASE
