Accession Number:

ADD014969

Title:

Method of Producing a Thin Silicon-On-Insulator Layer.

Descriptive Note:

Patent, Filed 29 Sep 89, patented 7 May 91,

Corporate Author:

DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s):

• Godbey, David J.
• Hughes, Harold L.
• Kub, Francis J.

Report Date:

1991-05-07

Pagination or Media Count:

8.0

Abstract:

A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy includes properly doping a prime silicon wafer for the desired application, growing a strained Si1-xironex alloy layer onto seed wafer to serve as an etch stop, growing a silicon layer on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer and a test wafer, bonding the oxide surfaces of the test and prime wafers, machining the backside of the prime wafer and selectively etching the same to remove the silicon, removing the strained alloy layer by a non-selective etch, thereby leaving the device region silicon layer. In an alternate embodiment, the process includes implanting germanium, tin or lead ions to form the strained etch stop layer.

Descriptors:

• ALLOYS
• DOPING
• ETCHING
• GERMANIUM
• IMPLANTATION
• IONS
• LAYERS
• MACHINING
• OXIDES
• REGIONS
• SELECTION
• SILICON
• SURFACES
• TEST AND EVALUATION
• THICKNESS
• THIN FILMS
• TIN
• WAFERS

Subject Categories:

• Solid State Physics
• Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE