High Speed Parallel Backplane.
Patent application, filed 29 Jan 90,
DEPARTMENT OF THE NAVY WASHINGTON DC
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This invention relates to high speed data processing in particular to a high speed parallel backplane for interconnecting a plurality of printed circuit boards in a parallel processing system. The conventional approach to parallel backplane design utilizes a set of circuit board connectors mounted on a flat supporting structure typically made of phenolic glass-epoxy. Common bus pins are interconnected via a set of linear metallized traces deposited on the supporting structure. Although this technique is acceptable for systems supporting low bandwidth exceeds 15 MHz. Of all the physical parameters which affect bus bandwidth, signal path length is the most crucial. According to the law of electromagnetics, when a signal path length approaches a quarter wavelength of operating frequency, radiative losses occur.
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