Process for Fabricating Self-Aligned Field Emitter Arrays.
Patent Application, Filed 2 Feb 90,
DEPARTMENT OF THE NAVY WASHINGTON DC
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This patent application discloses a process for fabricating self-aligned field emitter arrays using a self-leveling planarization technique, e.g. spin-on processes, is disclosed which includes the steps of depositing a dielectric layer on top of an array of field emitters, depositing a thin conducting film over the dielectric layer, and applying a planarization layer on the thin conducting film. Thereafter the structure is selectively etched until the underlying conducting layer is exposed in regions surrounding the field emitters, thereby defining the grid apertures. The conducting layer and dielectric layer are then selectively etched sequentially to a depth sufficient to expose a field emitter cathode tip at each field emitter site. This invention uses the concept of self-leveling, planarizing material to define the grid apertures. After defining the aperture hole size and location, then appropriate etching processes can form the apertures themselves thereby exposing the sharp field emitters which yield an integrally gridded three-dimensional field emitter array structure. Keywords Patents Serial number 473,752 N.C. 69,325 Field emission Electronics. jg
- Electricity and Magnetism