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Accession Number:
ADD014474
Title:
Design and Fabrication Sequence for InP Junction FETS and Junction HEMTS.
Descriptive Note:
Patent application filed 29 Dec 89,
Corporate Author:
DEPARTMENT OF THE NAVY WASHINGTON DC
Report Date:
1989-12-29
Pagination or Media Count:
25.0
Abstract:
This invention is directed to a novel process of fabricating indium phosphide junction field-effect transistors JFETs and indium phosphide junction high electron mobility transistors JHEMTs and more particularly to such processes which utilize a nitride-registered gate approach to obtain JFETs and JHEMTs having sub-micron gate lengths. The sub-micron gate semiconductor device includes source, drain, gate regions and a channel region connecting the source and drain regions. The fabrication sequence begins by growing a first insulating layer on a semiconductor structure including a substrate and a channel region. Next, source and drain regions are delineated through the first insulating layer and source and drain regions are implanted into a substrate. A second insulating layer is then grown on the first insulating layer. A photoresist layer is then applied and a gate photoresist opening is delineated above the second insulating layer. The first and second insulating layers are then patterned by anisotropic etching to limit the amount of undercutting while using the photoresist layer as a mask. A first ion selected from a group consisting of Phosphorus and Arsenic, and a second ion selected from the group consisting of Beryllium, Zinc, and Cadmium are sequentially implanted through the gate opening into the gate region down to the channel region. Keywords Ion implantation Epitaxial growth Patent applications. AW
Distribution Statement:
APPROVED FOR PUBLIC RELEASE