Process of Fabricating TiW/Si Self-Aligned Gate for GaAs MESFETs (Metal Silicon Field Effect Transistors).
Patent, Filed 6 Jun 85, patented 15 Dec 87,
DEPARTMENT OF THE AIR FORCE WASHINGTON DC
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A major difficulty with fabricating GaAs digital logic circuits using enhancement-mode MESFETs has been the large gate-source and gate-drain parasitic resistances inherent in conventional designs. A self-aligned gate process is presented, which incorporates a mushroom gate structure for self-aligning both an n implant and the sourcedrain contacts to the gate, thus minimizing the parasitic resistances. The mushroom gate consists of a two-layer TiWSi metallization in which the bottom TiW layer is undercut with a closely controllable chemical etch. The process is compatible with the high temperature anneal necessary to activate ion-implanted GaAs.
- Electrical and Electronic Equipment