Patent, Filed 30 Jun 87, patented 1 Mar 88,
DEPARTMENT OF THE NAVY WASHINGTON DC
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This document describes that is generally made up of master and slave data processors having master and slave microprocessors, master and slave multibit latches, and separate pairs of read only and random access memories for both the master and slave processors. A data inputoutput IO bus and an address bus are provided for interconnecting various elements of either the master or slave processors. An interface advantageously interconnects the slave data IO bus with the master data IO bus. The master microprocessor advantageously functions to selectively process the master parallel data input when received so that it is compatible with a serial data processor when the selectively processed parallel data input is converted to serial format by a parallel-to-serial-data converter. The master processor further functions by way of the interface to convert a slave parallel data input previously processed by the slave processor to serial form when the master processor is not busy in processing a parallel data input. The improved masterslave adaptor preferably handles two separate 32-bit parallel data inputs with either input being selectively processed and readily converted by the improved adaptor to a 32-bit serial format that is compatible with a serial data processor.
- Computer Hardware