Method of Characterizing Critical Timing Paths and Analyzing Timing Related Failure Modes in Very Large Scale Integrated Circuits.
Patent, Filed 28 Mar 85, patented 6 Oct 87,
DEPARTMENT OF THE AIR FORCE WASHINGTON DC
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A method for characterizing critical timing paths and analyzing timing related failure modes in high clock rate photocurrent at the drain of a single transistor in a very large scale integrated circuit. The laser testing apparatus utilized with the method of this invention incorporates therein a laser having its output beam focused onto the drain junction of the transistor under test. The localized injection of electromagnetic radiation produces a photocurrent at the drain junction of the transistor at specific times during the testing procedure which increases in the minimum operating power supply andor a decrease in the maximum operating frequency at which the microcircuit wil properly function. Consideration of these parameters and the level of photocurrent provide a measurement related to the worst case timing margin which occurs during the functional test of the integrated microcircuit.
- Electrical and Electronic Equipment