Intercept Resistant Data Transmission System.
Patent, Filed 25 Jun 82, patented 28 Apr 87,
DEPARTMENT OF THE NAVY WASHINGTON DC
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A secure communication system, which may be safely used even in the presence of an enemy interceptor, includes a transmitter and a receiver. The transmitter comprises a first modulo-2 adder, having as one input a sequence of N-bit binary numbers. A first random read-only memory ROM, comprises a plurality of storage cells. The input of the ROM is connected to the output of the modulo-2 adder. Each of the cells of the ROM, which have distinct addresses, contain a random number. The input to the ROM is a binary number representing a specific address, whereas the output of the ROM is a signal representing a random binary number. A delay line has its input connected to the output of the random read-only memory, its output constituting the second input to the modulo-2 adder. A second random ROM, having the same type of hardware but different random content, has its input connected to the output of the delay line. A second modulo-2 adder has its two inputs connected to the outputs of the first and second random read-only memories, the sequence of binary bits to be transmitted appearing at its output. Another component of the transmitter is a buffer memory, whose input and output are connected to the output of the second modulo-2 adder, the sequence of binary words to be transmitted appearing at the output of the second modulo-2 adder.
- Command, Control and Communications Systems