Patent, Filed 19 Nov 80, patented 8 Nov 83,
DEPARTMENT OF THE NAVY WASHINGTON DC
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The architecture of a special-purpose multiprocessor, hierarchically structured and functionally distributed, having distributed cache memory for local processing and a common applications task manager in each microcomputer. a group of identical microcomputers execute the total program in an intrinsically parallel mode within the frame times scheduled by a system state control microcomputer.
- Computer Hardware