Accession Number:

ADD013225

Title:

Dual-Gate Deep-Depletion Technique for Carrier-Generation-Lifetime Measurement.

Descriptive Note:

Patent, Filed 6 Mar 81, patented 10 Jan 84,

Corporate Author:

DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s):

Report Date:

1984-01-10

Pagination or Media Count:

6.0

Abstract:

This patent discloses a method for investigating the quality of dielectrically isolated thin film semiconductor layers in inversion-mode MOS devices having dual-gate control capabilities which allow two channels to be created in the semiconductor film. With one channel conducting and a drain voltage providing operation in the saturation region, a step voltage is applied to the gate associated with the second channel which has a transient effect on the current in the first channel. This transient may be analyzed to measure the generation lifetime and other parameters in the body of the device.

Subject Categories:

  • Solid State Physics
  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE