Method of Making a Planar INP Insulated Gate Field Effect Transistor by a Virtual Self-Aligned Process.
DEPARTMENT OF THE NAVY WASHINGTON DC
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This patent discloses a planar compound semiconductor insulated gate field effect transistor and a virtual self-aligned process for making the same. The device includes a semi-insulating Indium Phosphide substrate in which doped source and drain regions separated by a channel region are located. An insulated gate is located on the surface of the substrate over the channel region. The device is fabricated by a virtual or partially self-aligned method wherein the channel region is defined by forming channel alignment layers, are formed in the substrate by ion-implantation. The remainder of the device is formed on the surface of the substrate.
- Solid State Physics