Tri-State Type Driver Circuit.
DEPARTMENT OF THE AIR FORCE WASHINGTON DC
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An FET complementary pair provides the output to a data line. A data input line is coupled to the gate of the P-FET via an OR gate configuration, and to the gate of the N-FET via an AND gate configuration. The output of each gate configuration is cross-connected to an input of the other. When the input data state changes, the two gate configurations provide delays which are effectively in tandem, so that the FET which was ON is first turned OFF, and after a short delay the other is turned ON. This delay ensures that both FETs are not ON at the same time, which prevents an undesirable power flow. To provide a high impedance float state, an enable input and its complement are connected to the AND and OR gate configurations respectively. Author
- Electrical and Electronic Equipment
- Solid State Physics
- Non-Radio Communications