Accession Number:

ADD010825

Title:

Accumulation-Mode in O.53 Ga 0.47 as Field Effect Transistor.

Descriptive Note:

Patent Application,

Corporate Author:

DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s):

Report Date:

1983-10-03

Pagination or Media Count:

9.0

Abstract:

The invention is a normally-off, accumulation mode field-effect-transistor FET utilizing a positive bias on an insulated gate to induce a conducting channel between source and drain ohmic contacts. The device is fabricated on an epitaxial layer of semi-insulating In0.53Ga0.47As. The semi-insulating layer of In0.53Ga0.47As is epitaxially deposited upon a semi-insulating InP substrate. Ohmic source and drain contacts are formed at separate regions upon the free surface of the semi-insulating In0.53Ga0.47As layer. Electrical connections to an external circuit are made to the ohmic source and drain contacts. A dielectric layer of either Si02 or Al203 is deposited over the entire remaining surface of the In0.53Ga0.47As layer. A gate electrode is formed upon the dielectric insulating layer wherein said gate electrode extends up to the source and drain contacts so that the conducting channel formed by the accumulation layer would form a complete path from source to drain. The gate electrode also contains means to be electrically connected to an external electronic circuit. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE