Normally Off InP Field Effect Transistor Making Process.
DEPARTMENT OF THE NAVY WASHINGTON DC
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A normally off insulated gate field effect transistor having a p-type single crystal InP substrate with source and drain contacts spaced apart and disposed thereon with a layer of silicon dioxide disposed over the InP material in the space between the contacts and a gate electrode disposed on the silicon dioxide to completely bridge space between the contacts. The p-type single crystal InP substrate may be replaced by a p-type epitaxial InP material disposed on a semi-insulating InP substrate. Author
- Electrical and Electronic Equipment
- Solid State Physics