Accession Number:

ADD010153

Title:

Silicon Barrier Josephson Junction Configuration.

Descriptive Note:

Patent,

Corporate Author:

DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s):

Report Date:

1983-01-11

Pagination or Media Count:

5.0

Abstract:

A planar, silicon barrier, Josephson junction and method of forming the junction which does not require expensive high-resolution lithography techniques such as electron beam or x-ray. The method includes an etching mask-etch process which forms the basic structure configuration using a 110-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE