High Speed Sample and Hold Circuit.
DEPARTMENT OF THE NAVY WASHINGTON DC
Pagination or Media Count:
A high speed sample and hold circuit which holds the peak value of a narrow pulse for a period of time at least three orders of magnitude larger than the pulse duration. The circuit is constructed with a diode bridge having an input, an output a first drive corner and a second drive corner. The diode bridge is switched on by two transistors configured as a high speed, pulsed current source and connected to the first and second drive corners of the bridge. The bridge is reverse biased by two resistors which are also connected to the first and second drive corners such that each resistor is in series with the bridge but is in parallel with the transistors. The circuit is provided with a storage capacitor in the output of the bridge which is isolated from the output load by a buffer. In operation, the transistors are turned on by simultaneous voltage pulses, the transistors then supply high speed, pulsed current to the bridge and the bridge is switched on and balanced. When a transient voltage signal to be sampled is supplied to the bridge input, the bridge becomes unbalanced such that current flows in or out of the storage capacitor until the bridge is unbalanced. Author
- Electrical and Electronic Equipment