Tape Automated Bonding Test Board.
DEPARTMENT OF THE ARMY WASHINGTON DC
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There is disclosed a universal electrical conductor pattern for both multilayer and single layer test substrates for tape bonded hybrids which is adapted to accept semiconductor chips of various sizes and numbers of leads. The pattern consists of four sets of equally spaced parallel rectangularly shaped outer lead bonding pads which are orthogonally arranged in a repetitive sequence around a chip bonding pad. Each set of outer lead bonding pads consists of a first subset of six like pads arranged adjacently in registration along one edge of the chip bonding pad, and second and third subsets of two outer lead bonding pads each arranged on either side of said first subset in parallel relationship therewith but set back from the corners of the chip bonding pad. The rectangularly shaped outer lead bonding pads extend away from the respective edges of the chip bonding pad a predetermined distance so as to accommodate either twenty four, thirty two or forty pin lead frames having a standard twenty mil lead spacing. Author
- Electrical and Electronic Equipment