Automatic Bias Adjustment Circuit for a Successive Ranged Analog/Digital Converter.
DEPARTMENT OF THE AIR FORCE WASHINGTON DC
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This report describes an automatic bias adjustment circuit for a successive ranged analogdigital converter SRADC that eliminates the need for manual bias adjustments and calibration inputs. The bias correction circuit comprehends dual flip flops that are triggered by selected comparators of the SRADC n bit parallel analogdigital converter. The flip flop output signals control updown counters whose output bits drive digitalanalog converter. The digitalanalog converted signals are introduced back into the SRADC analog chain to zero bias errors in a particular sub-range. A disabling circuit prevents operation of the bias adjustment circuits for the first sub-range. Author
- Electrical and Electronic Equipment