Accession Number:

ADD005997

Title:

Failureresistant Pseudo-Nonvolatile Memory.

Descriptive Note:

Patent,

Corporate Author:

DEPARTMENT OF THE NAVY WASHINGTON DC

Report Date:

1979-01-02

Pagination or Media Count:

5.0

Abstract:

Disclosed is a plurality of parallel resistive-capactive clamping circuits individually coupling the bit input and bit output terminals of a multi-bit, serialparallel SP, synchronousasynchronous SA shift register e.g., CD-4034A. The clamping circuits provide the contents of the shift register with an increased immunity from the effects of transients, radiation, and temporary power failures. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE