Digital Bypassable Register Interface.
DEPARTMENT OF THE NAVY WASHINGTON D C
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This patent discloses an interface for transmitting data in either a clock edge triggered synchronous transmission mode or an asynchronous transmission mode. An edge triggered register has its input connected to a source of digital data and its output connected to a two-to-one multiplexer. A bypass path connected between the digital data source and the multiplexer is provided around the edge triggered register. The two-to-one multiplexer is selectively actuable to provide either asynchronous transmission by connecting the bypass path to an output means or to provide synchronous transmission by connecting the output of the edge triggered register to the output means. Author
- Electrical and Electronic Equipment