Stabilized Delay Line Oscillator.
DEPARTMENT OF THE NAVY WASHINGTON D C
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This patent describes a device and technique for providing stability to a coherent delay line clock. A voltage controllable delay is combined with the lumped delay line of a coherent delay line clock to enable the control of the period of the clock. The voltage controllable delay is obtained by comparing the clock count during a predetermined time period against a fixed number N to obtain a difference count. The difference count is then integrated to form a bias voltage for control of the additional delay. The delay line period will then be a ratio of the predetermined period to the fixed number N, which number may be digitally modified to provide a source of variable frequency. Author
- Electrical and Electronic Equipment