Two's Complement Subtracting System.
DEPARTMENT OF THE AIR FORCE WASHINGTON D C
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The patent relates to a twos complement subtractor using a one bit full adder for the most significant bit. A series of arithmetic logic units are fed by the respective binary bits to be subtracted with the logic units effecting internal twos complementing of the subtrahend thereby permitting adding to the minuend. The most significant input bits are in addition fed to a one bit full adder together with the carry in bit from the last arithmetic logic unit of the series. The one bit full adder outputs the most significant bit or the sign resulting from the subtraction and this adder can have either internal inversion of the subtrahend or an inverter can precede the subtrahend input.
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