DEPARTMENT OF THE NAVY WASHINGTON D C
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The patent describes a high-speed adder circuit capable of performing addition with binary numbers in 1s complement, 2s complement or sign-magnitude formats. The adder can be made in the form of a single chip that can be assembled in multiple units to expand its capacity. There is a provision for converting minus zero to plus zero so as to prevent oscillations from occurring in the loop circuit. Also, the sum output is automatically shifted to the correct format when an overflow condition occurs.
- Computer Hardware