High-Frequency CCD Adder and Multiplier.
DEPARTMENT OF THE NAVY WASHINGTON D C
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The patent application describes a device for implementing the arithmetic operations of addition and multiplication utilizing CCD concepts and MOSFET properties. First and second CCD channels convert first and second input voltages into first and second charge quantities, respectively. The first and second charge quantities are added in a third CCD channel to provide a third charge quantity linearly proportional to the sum of the first and second input voltages. The three charge quantities are sensed by three floating gate amplifiers operated in the saturation region. The outputs of the floating gate amplifiers are subsequently combined by a differential amplifier, the output of which is linearly proportional to the product of the first and second input voltages.
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